The present invention relates to a method and/or architecture for low power oscillators generally and, more particularly, to a method and/or architecture for low operating voltage crystal oscillators.
Referring to FIG. 1, a circuit 10 is shown implementing a conventional oscillator. The circuit 10 generally comprises a circuit 12, a resistor 14, a capacitor C1, and a capacitor C2. An input signal (i.e., XTIN) is presented to the circuit 12 and to a first side of the capacitor C1. An output signal (i.e., XTOUT) is presented from the circuit 12 and to a first side of the capacitor C2. A second side of both the capacitors C1 and C2 is coupled to ground. The conventional oscillator 10 is implemented as an external oscillator configured to receive the node XTIN and present the node XTOUT.
The resistor 14 has a large resistance to reduce power consumption of the circuit 12. Additionally, a large independent external resistance (not shown) is coupled between the signal XTIN and the signal XTOUT for biasing the gain of the inverter 12. The biasing of the circuit 10 is supply dependent. Supply dependent biasing increases the parts per million (ppm) variations of the clock. The output of the circuit 10 is not easily translated to a rail to rail signal. The non-linear capacitance (C1 and C2) adds to the ppm variations. The circuit 10 has difficulties with low power supply voltages.
The present invention concerns an apparatus comprising a first circuit and a capacitor circuit. The first circuit may be configured to generate an output signal having a frequency in response to (i) an input signal having a reference frequency and (ii) one or more adjustment signals. The capacitor circuit may be configured to adjust the frequency of the output signal. The one or more adjustment signals may provide constant current biasing of the first circuit.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing low operating voltage crystal oscillators that may (i) introduce less variations in gain of the gain stage of an oscillator for a large variation in the power supply voltage (e.g., 1.8-3.6V); (ii) provide current controlled biasing in both the power and ground path; (iii) control the amplitude growth; (iv) tune the capacitance structure while introducing minimal ppm variations; (v) provide easy translation to rail-to-rail logic; and/or (vi) operate with low supply voltages.